library ieee;
use ieee.std_logic_1164.all;

entity testbench_register_n is
end testbench_register_n;

architecture test of testbench_register_n is

	constant N 		: integer := 4;
	constant PERIOD : time	  := 10 ns;

	component register_n
		generic ( N : integer := 4 );
		port (
			clk_i 	 : in  std_logic;
			nreset_i : in  std_logic;
			we_i	 : in  std_logic;
			d_i      : in  std_logic_vector(N-1 downto 0);
			q_o      : out std_logic_vector(N-1 downto 0)
		);
	end component;

	signal clk      : std_logic;
	signal nreset	: std_logic;
	signal we 		: std_logic;
	signal d	  	: std_logic_vector(N-1 downto 0);
	signal q 		: std_logic_vector(N-1 downto 0);

begin

	register_n_inst : register_n
		generic map ( 
			N => N
		) port map (
			clk_i 	 => clk, 
			nreset_i => nreset,
			we_i	 => we,
			d_i      => d,
			q_o      => q
		);

	gen_clk : process
	begin
		clk <= '0';
		wait for PERIOD/2;
		clk <= '1';
		wait for PERIOD/2;
	end process;

	gen_test : process
	begin
		wait for (PERIOD*4);

		nreset <= '0';

		wait for (PERIOD);

		nreset 	<= '1';
		we 		<= '1';
		d	  	<= X"A";

		wait for (PERIOD);

		nreset 	<= '1';
		we 		<= '0';
		d	  	<= X"C";

		wait for (PERIOD);

		nreset 	<= '1';
		we 		<= '1';
		d	  	<= X"8";

		wait;
	end process;

end test;
